View MAX9240A_8811976.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the MAX9240A compact deserializer is designed to interface with a gmsl serializer over 50 coax or 100 shielded twisted-pair (stp) cable. the device pairs with the max9271 or max9273 serializers. the parallel output is programmable for single or double output. double output strobes out half of a parallel word on each pixel clock cycle. double output can be used with gmsl serializers that have the double-input feature. the device features an embedded control channel that operates at 9.6kbps to 1mbps. using the control chan - nel, a microcontroller (c) can program the serializer/ deserializer and peripheral device registers at any time, independent of video timing. two programmable gpio ports and a continuously sampled gpi input are available. for use with longer cables, the device has a program - mable equalizer. programmable spread spectrum is avail - able on the parallel output. the serial input meets iso 10605 and iec 61000-4-2 esd standards. the core sup - ply range is 1.7v to 1.9v and the i/o supply range is 1.7v to 3.6v. the device is available in a 48-pin (7mm x 7mm) tqfn-ep package with 0.5mm lead pitch and operates over the -40c to +105c temperature range. applications automotive camera systems beneits and features ideal for camera applications ? works with low-cost 50 coax cable and fakra connectors or 100 stp ? error detection/correction ? 9.6kbps to 1mbps control channel in i 2 c-to-i 2 c mode with clock stretch capability ? best-in-class supply current: 90ma (max) ? double-rate clock for megapixel cameras ? cable equalization allows 15m cable at full speed ? 48-pin (7mm x 7mm) tqfn-ep package with 0.5mm lead pitch high-speed data deserialization for megapixel cameras ? up to 1.5gbps serial-bit rate with single or double output: 6.25mhz to 100mhz clock multiple control-channel modes for system flexibility ? 9.6kbps to 1mbps control channel in uart-to- uart or uart-to-i 2 c modes reduces emi and shielding requirements ? programmable spread spectrum on the parallel output reduces emi ? tracks spread spectrum on serial input peripheral features for camera power-up and verification ? built-in prbs checker for ber testing of the serial link ? fault detection of serial link shorted together, to ground, to battery, or open ? two gpio ports ? dedicated up/down gpi for camera frame sync trigger and other uses ? remote/local wake-up from sleep mode meets rigorous automotive and industrial requirements ? -40c to +105c operating temperature ? 10kv contact and 15kv air iec 61000-4-2 esd protection ? 10kv contact and 30kv air iso 10605 esd protection ordering information appears at end of data sheet. typical application circuit appears at end of data sheet. 19-7319; rev 1; 8/15 MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect evaluation kit available downloaded from: http:///
MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 2 general description ............................................................................ 1 applications .................................................................................. 1 benefits and features .......................................................................... 1 absolute maximum ratings* ..................................................................... 6 package thermal characteristics ................................................................. 6 dc electrical characteristics ..................................................................... 6 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 typical operating characteristics ................................................................. 11 pin configuration ............................................................................. 13 pin description ............................................................................... 14 functional diagram ........................................................................... 16 detailed description ........................................................................... 21 register mapping ................................................... ........................ 21 bit map ................................................... ................................ 21 serial link signaling and data format ................................................... ........ 25 reverse control channel ................................................... .................. 25 data-rate selection ................................................... ...................... 25 control channel and register programming ................................................... .................... 26 uart interface ................................................... .......................... 26 interfacing command-byte-only i 2 c devices with uart ................................................... ................. 27 uart bypass mode ................................................... ................... 27 i 2 c interface ................................................... ............................ 27 start and stop conditions .................................................. ............. 29 bit transfer ................................................... ........................... 29 acknowledge .................................................. .......................... 29 slave address .................................................. ......................... 30 bus reset ................................................... ............................ 30 format for writing .................................................. ...................... 30 format for reading ................................................... .................... 30 i 2 c communication with remote-side devices ................................................. 31 i 2 c address translation .................................................. .................... 31 control-channel broadcast mode ................................................... ........... 31 gpo/gpi control ................................................... ........................ 31 prbs test ................................................... .............................. 32 line equalizer ................................................... ........................... 32 spread spectrum ................................................... ........................ 32 table of contents downloaded from: http:///
MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 3 manual programming of the spread-spectrum divider ................................................... ............. 32 additional error detection and correction ................................................... ..... 33 cyclic redundancy check (crc) ................................................... ........ 33 hamming code ................................................... ....................... 33 hs/vs encoding and/or tracking ................................................... ............ 33 serial input ................................................... ............................. 33 coax-mode splitter ................................................... ....................... 33 cable type configuration input (cx/tp) .................................................. ....... 34 sleep mode ................................................... ............................. 34 power-down mode .................................................. ........................ 34 configuration link ................................................... ........................ 34 link startup procedure ........................................................................ 35 applications information ........................................................................ 37 error checking ................................................... .......................... 37 err output ................................................... ............................. 37 autoerror reset ................................................... .......................... 37 dual c control ................................................... ......................... 37 changing the clock frequency ................................................... .............. 37 fast detection of loss-of-synchronization ................................................... ................... 37 providing a frame sync (camera applications) ................................................... ..................... 38 software programming of the device addresses ................................................... ................... 38 three-level configuration inputs ................................................... ............ 38 configuration blocking ................................................... .................... 38 compatibility with other gmsl devices ................................................... ....... 38 gpios ................................................... ................................. 38 staggered parallel outputs ................................................... ................. 38 local control-channel enable (lccen) ................................................... ...... 39 line-fault detection .................................................. ....................... 39 internal input pulldowns ................................................... ................... 40 choosing i 2 c/uart pullup resistors ................................................... ........ 40 ac-coupling .................................................. ............................. 40 selection of ac-coupling capacitors ................................................... ......... 40 power-supply circuits and bypassing .................................................. ......... 40 power-supply table ................................................... ...................... 40 table of contents ( continued) downloaded from: http:///
MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 4 cables and connectors ................................................... ................... 40 board layout ................................................... ............................ 41 esd protection ................................................... .......................... 41 typical application circuit ...................................................................... 48 ordering information .......................................................................... 48 chip information .............................................................................. 48 package information .......................................................................... 48 revision history .............................................................................. 49 figure 1. reverse control-channel output parameters ............................................... 17 figure 2. test circuit for differential input measurement .............................................. 18 figure 4. line fault ........................................................................... 18 figure 3. test circuit for single-ended input measurement ............................................ 18 figure 5. worst-case pattern output ............................................................. 19 figure 6. parallel clock output high and low times ................................................. 19 figure 7. i 2 c timing parameters ................................................................. 19 figure 8. output rise-and-fall times ............................................................. 20 figure 9. deserializer delay ..................................................................... 20 figure 10. gpi-to-gpo delay ................................................................... 20 figure 11. lock time .......................................................................... 21 figure 12. power-up delay ..................................................................... 21 figure 13. single-output waveform (serializer using single input) ...................................... 22 figure 14. single-output waveform (serializer using doubl e input) ..................................... 22 figure 15. double-output waveform (serializer using single input) ..................................... 23 figure 16. double-output waveform (serializer using doubl e input) ..................................... 23 figure 17. serial-data format ................................................................... 25 figure 18. gmsl uart protocol for base mode .................................................... 26 figure 19. gmsl uart data format for base mode ................................................. 27 figure 20. sync byte (0x79) .................................................................... 27 figure 21. ack byte (0xc3) ..................................................................... 27 figure 22. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 0) ........ 28 figure 23. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 1) ........ 28 figure 24. start and stop conditions ........................................................... 29 figure 25. bit transfer ......................................................................... 29 figure 26. acknowledge ........................................................................ 29 figure 27. slave address ....................................................................... 30 table of contents ( continued) list of figures downloaded from: http:///
MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 5 table 1. output map ........................................................................... 24 table 2. data-rate selection table ............................................................... 25 table 3. i 2 c bit-rate ranges ................................................................... 31 table 4. cable equalizer boost levels ............................................................ 32 table 5. parallel output spread .................................................................. 32 table 6. modulation coefficients and maximum sdiv se ttings ......................................... 32 table 7. configuration input map ................................................................. 34 table 8. startup procedure for video-display applications ............................................ 35 table 9. startup procedure for image-sensing applications ........................................... 36 table 10. MAX9240A feature compatibility ........................................................ 38 table 11. staggered output delay ................................................................ 39 table 12. double-function configuration .......................................................... 39 table 13. line fault mapping .................................................................... 39 table 14. typical power-supply currents (using worst-case i nput pattern) ............................... 40 table 15. suggested connectors and cables for gmsl ............................................... 40 table 16. register table ....................................................................... 42 figure 28. format for i 2 c write .................................................................. 30 figure 29. format for write to multiple registers .................................................... 30 figure 30. format for i 2 c read .................................................................. 31 figure 31. 2:1 coax-mode splitter connection diagram ............................................... 34 figure 32. coax-mode connection diagram ........................................................ 34 figure 33. state diagram, remote microcontroller application ......................................... 36 figure 34. human body model esd test circuit ...................................................... 41 figure 35 iec 61000-4-2 contact discharge esd test circuit ........................................... 41 figure 36. iso 10605 contact discharge esd test circuit ............................................. 41 list of figures ( continued) list of tables downloaded from: http:///
avdd to ep.............................................................-0.5v to +1.9v dvdd to ep...........................................................-0.5v to +1.9v iovdd to ep..........................................................-0.5v to +3.9v in+, in- to ep.........................................................-0.5v to +1.9v lmn_ to ep (15ma current limit).........................-0.5v to +3.9v all other pins to ep................................-0.5v to (v iovdd + 0.5v) in+, in- short circuit to ground or supply .................continuous continuous power dissipation (t a = +70c) tqfn (derate 40mw/c above +70c).....................3200mw junction temperature......................................................+150c operating temperature range......................... -40c to +105c storage temperature range............................. -65c to +150c lead temperature (soldering, 10s).................................+300c soldering temperature (reflow).......................................+260c tqfn junction-to-ambient thermal resistance ( ja )...........25c/w junction-to-case thermal resistance ( jc )..................1c/w (note 1) (v avdd = v dvdd = 1.7v to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground, t a = -40c to +105c, unless otherwise noted. typical values are at v avdd = v dvdd = v iovdd = 1.8v, t a = +25c.)(note 2) * ep is connected to pcb ground. parameter symbol conditions min typ max units single-ended inputs (i2csel, lccen, gpi, pwdn , ms/hven) high-level input voltage v ih1 0.65 x v iovdd v low-level input voltage v il1 0.35 x v iovdd v input current i in1 v in = 0v to v iovdd -10 +20 a three-level logic inputs (cx/tp) high-level input voltage v ih 0.7 x v iovdd v low-level input voltage v il 0.3 x v iovdd v mid-level input current i inm (note 3) -10 +10 a input current i in -150 +150 a single-ended outputs (dout_, pclkout) high-level output voltage v oh1 i out = -2ma dcs = 0 v iovdd - 0.3 v dcs = 1 v iovdd - 0.2 low-level output voltage v ol1 i out = 2ma dcs = 0 0.3 v dcs = 1 0.2 MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 6 note 1: package thermal resistances were obtained using the method described in jedec specification jesd51- 7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . absolute maximum ratings* stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristicsdc electrical characteristics downloaded from: http:///
(v avdd = v dvdd = 1.7v to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground, t a = -40c to +105c, unless otherwise noted. typical values are at v avdd = v dvdd = v iovdd = 1.8v, t a = +25c.)(note 2) parameter symbol conditions min typ max units output short-circuit current i os dout_ v o = 0v, dcs = 0 v iovdd = 3.0v to 3.6v 15 25 39 ma v iovdd = 1.7v to 1.9v 3 7 13 v o = 0v, dcs = 1 v iovdd = 3.0v to 3.6v 20 35 63 v iovdd = 1.7v to 1.9v 5 10 21 pclkout v o = 0v, dcs = 0 v iovdd = 3.0v to 3.6v 15 33 50 v iovdd = 1.7v to 1.9v 5 10 17 v o = 0v, dcs = 1 v iovdd = 3.0v to 3.6v 30 54 97 v iovdd = 1.7v to 1.9v 9 16 32 open-drain inputs/outputs (gpio0/dbl, gpio1/bws, rx/sda/edc, tx/scl/es, err , lock, lflt) high-level input voltage v ih2 0.7 x v iovdd v low-level input voltage v il2 0.3 x v iovdd v input current i in2 (note 4) rx/sda, tx/scl -110 +5 a lock, err , gpio_, lflt -80 +5 dbl, bws, edc, es -10 +20 low-level output voltage v ol2 i out = 3ma v iovdd = 1.7v to 1.9v 0.4 v v iovdd = 3.0v to 3.6v 0.3 output for reverse control channel (in+, in-) differential high output peak voltage, (v in +) - (v in -) v roh no high-speed data transmission (figure 1) 30 60 mv differential low output peak voltage, (v in +) - (v in -) v rol no high-speed data transmission (figure 1) -60 -30 mv differential inputs (in+, in-) differential high input threshold (peak) voltage, (v in +) - (v in -) v idh(p) (figure 2) activity detector, medium threshold (0x22 d[6:5] = 01) 60 mv activity detector, low threshold (0x22 d[6:5] = 00) 45 differential low input threshold (peak) voltage, (v in +) - (v in -) v idl(p) (figure 2) activity detector, medium threshold (0x22 d[6:5] = 01) -60 mv activity detector, medium threshold (0x22 d[6:5] = 00) -45 input common-mode voltage ((v in +) + (v in -))/2 v cmr 1 1.3 1.6 v differential input resistance (internal) r i 80 105 130 ? MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 7 dc electrical characteristics (continued) downloaded from: http:///
(v avdd = v dvdd = 1.7v to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground, t a = -40c to +105c, unless otherwise noted. typical values are at v avdd = v dvdd = v iovdd = 1.8v, t a = +25c.)(note 2) parameter symbol conditions min typ max units single-ended inputs (in+, in-)single-ended high input threshold (peak) voltage v ish(p) activity detector, medium threshold (0x22 d[6:5] = 01) (figure 3) 43 mv activity detector, low threshold (0x22 d[6:5] = 00) (figure 3) 33 single-ended low input threshold (peak) voltage v isl(p) activity detector, medium threshold (0x22 d[6:5] = 01) (figure 3) -43 mv activity detector, medium threshold (0x22 d[6:5] = 00) (figure 3) -33 input resistance (internal) r i 40 52.5 65 ? line fault detection input (lmn0, lmn1) short-to-gnd threshold v tg (figure 4) 0.3 v normal threshold v tn (figure 4) 0.57 1.07 v open threshold v to (figure 4) 1.45 v io + 0.06 v open input voltage v io (figure 4) 1.47 1.75 v short-to-battery threshold v te (figure 4) 2.47 v power supply worst-case supply current (figure 5) i wcs bws = 0, single output, eq off f pclkout = 25mhz 42 65 ma f pclkout = 50mhz 61 90 bws = 0, double output, eq off f pclkout = 50mhz 42 70 f pclkout = 100mhz 62 90 sleep mode supply current i ccs 50 100 a power-down current i ccz pwdn = ep 15 70 a esd protectionin+, in- (note 5) v esd human body model, r d = 1.5k?, c s = 100pf 8 kv iec 61000-4-2, r d = 330?, c s = 150pf contact discharge 10 air discharge 15 iso 10605, r d = 2k? , c s = 330pf contact discharge 10 air discharge 30 all other pins (note 6) v esd human body model, r d = 1.5k? , c s = 100pf 4 kv MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 8 dc electrical characteristics (continued) downloaded from: http:///
(v avdd = v dvdd = 1.7v to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground, t a = -40c to +105c, unless otherwise noted. typical values are at v avdd = v dvdd = v iovdd = 1.8v, t a = +25c.)(note 2) parameter symbol conditions min typ max units parallel clock output (pclkout) clock frequency f pclkout bws = 0, drs = 1 8.33 16.66 mhz bws = 0, drs = 0 16.66 50 bws = 1, drs = 1 6.25 12.5 bws = 1, drs = 0 12.5 37.5 bws = 1, drs = 0, 15-bit double input 25 75 bws = 0, drs = 0, 11-bit double input 33.33 100 clock duty cycle dc t high /t t or t low /t t (figure 6, note 7) 40 50 60 % clock jitter t j period jitter, peak to peak, spread off, 1.5gbps, prbs pattern, ui = 1/f pclkout (note 7) 0.05 ui i 2 c/uart port timing i 2 c/uart bit rate 9.6 1000 kbps output rise time t r 30% to 70%, c l = 10pf to 100pf, 1k? pullup to v iovdd 20 120 ns output fall time t f 70% to 30%, c l = 10pf to 100pf, 1k? pullup to v iovdd 20 120 ns input setup time t set i 2 c only (figure 6, note 7) 100 ns input hold time t hold i 2 c only (figure 6, note 7) 0 ns switching characteristics pclkout rise-and-fall time t r , t f 20% to 80%, v iovdd = 1.7v to 1.9v (note 7) dcs = 1, c l = 10pf 0.4 2.2 ns dcs = 0, c l = 5pf 0.5 2.8 20% to 80%, v iovdd = 3.0v to 3.6v (note 7) dcs = 1, c l = 10pf 0.25 1.7 dcs = 0, c l = 5pf 0.3 2.0 parallel data rise-and-fall time (figure 8) t r , t f 20% to 80%, v iovdd = 1.7v to 1.9v (note 7) dcs = 1, c l = 10pf 0.5 3.1 ns dcs = 0, c l = 5pf 0.6 3.8 20% to 80%, v iovdd = 3.0v to 3.6v (note 7) dcs = 1, c l = 10pf 0.3 2.2 dcs = 0, c l = 5pf 0.4 2.4 deserializer delay t sd (figure 9, notes 7, 8) spread spectrum enabled 6960 bits spread spectrum disabled 2160 reverse control-channel output rise time t r no forward-channel data transmission (figure 1, note 7) 180 400 ns reverse control-channel output fall time t f no forward-channel data transmission (figure 1, note 7) 180 400 ns MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 9 ac electrical characteristics downloaded from: http:///
note 2: limits are 100% production tested at t a = +105c. limits over the operating temperature range and relevant supply volt - age range are guaranteed by design and characterization. note 3: to provide a midlevel, leave the input open, or, if driven, put driver in high impedance. high-impe dance leakage current must be less than 10a. note 4: i in min due to voltage drop across the internal pullup resistor. note 5: specified pin to ground. note 6: specified pin to all supply/ground. note 7: guaranteed by design and not production tested. note 8: measured in serial link bit times. bit time = 1/(30 x f pclkout ) for bws = gnd. bit time = 1/(40 x f pclkout ) for bws = 1. (v avdd = v dvdd = 1.7v to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), ep connected to pcb ground, t a = -40c to +105c, unless otherwise noted. typical values are at v avdd = v dvdd = v iovdd = 1.8v, t a = +25c.)(note 2) parameter symbol conditions min typ max units gpi-to-gpo delay t gpio deserializer gpi to serializer gpo (cable delay not included) (figure 10) 350 s lock time t lock (figure 11, note 7) spread spectrum enabled 1.5 ms spread spectrum disabled 1 power-up time t pu (figure 12) 6 ms MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 10 ac electrical characteristics (continued) downloaded from: http:///
(v avdd = v dvdd = v iovdd = 1.8v, dbl = low, t a = +25c, unless otherwise noted.) supply current vs. pclkout frequency (bws = 1) MAX9240A toc02 pclkout frequency (mhz) supply current (ma) 10 15 20 30 25 35 40 45 50 55 60 65 70 7535 5 40 eq on prbs on, ss off, coax mode eq off supply current vs. pclkout frequency (bws = 0) MAX9240A toc03 pclkout frequency (mhz) supply current (ma) 45 40 10 15 20 30 25 35 65 5 50 40 45 50 55 60 35 prbs on, eq off, coax mode ss off ss on 10 15 20 30 25 35 40 supply current vs. pclkout frequency (bws = 1) MAX9240A toc04 pclkout frequency (mhz) supply current (ma) 60 5 35 prbs on, eq off, coax mode ss off ss on 40 45 50 55 output power spectrum vs. pclkout frequency (various spread) MAX9240A toc05 pclkout frequency (mhz) output power spectrum (dbm) 21.0 20.5 20.0 19.5 19.0 -80 -70 -60 -60 -40 -30 -20 -10 0 -90 18.5 21.5 f pclkout = 20mhz 0% spread 1% spread 2% spread 4% spread supply current vs. pclkout frequency (bws = 0) pclkout frequency (mhz) supply current (ma) 45 40 10 15 20 30 25 35 40 45 50 55 60 65 70 7535 5 50 eq on eq off prbs on, ss off, coax mode MAX9240A toc01 output power spectrum vs. pclkout frequency (various spread) MAX9240A toc06 pclkout frequency (mhz) output power spectrum (dbm) 52 51 50 49 48 -80 -70 -60 -60 -40 -30 -20 -10 0 -100 -90 47 53 f pclkout = 50mhz 0% spread 2% spread 4% spread MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect maxim integrated 11 www.maximintegrated.com typical operating characteristics downloaded from: http:///
(v avdd = v dvdd = v iovdd = 1.8v, dbl = low, t a = +25c, unless otherwise noted.) serial link switching pattern with 6db preemphasis (paralell bit rate = 50mhz, 10m stp cable) MAX9240A toc07 200ps /div 1.5gbps 50mv/div MAX9240A toc08 200ps/div 1.5gbps 50mv/div serial link switching pattern with 6db preemphasis (paralell bit rate = 50mhz, 20m coax cable) pclkout frequency (mhz) 20 40 60 0 maximum pclkout frequency vs. stp cable length (ber 10- 10 ) MAX9240A toc09 stp cable length (m) 15 10 5 0 20 no pe, eq off no pe, 10.7db eq 6db pe, eq off optimum pe/eq settings ber can be as low as 10 -12 for cable lengths less than 10m pclkout frequency (mhz) 20 40 60 0 maximum pclkout frequency vs. coax cable length (ber 10- 10 ) MAX9240A toc10 coax cable length (m) 15 20 10 5 0 25 no pe, eq off no pe, 10.7db eq 6db pe, eq off ber can be as low as 10 -12 for cable lengths less than 10m pclkout frequency (mhz) 2010 30 40 50 60 0 maximum pclkout frequency vs. additional differential c l (ber 10- 10 ) MAX9240A toc11 additional differential load capacitance (pf) 6 8 4 2 0 10 no pe, eq off no pe, 10.7db eq 6db pe, eq off ber can be as low as 10 -12 for c l < 4pf for optimum pe/eq settings 10m stp cable optimum pe/eq settings MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect maxim integrated 12 www.maximintegrated.com typical operating characteristics (continued) downloaded from: http:///
top view tqfn (7mm x 7mm x 0.75mm) connect ep to ground plane 13 14 15 16 17 18 19 20 21 22 23 24 pwdn + err lock lmn0 lmn1 lflt dout24/vs1 iovdd dout23/hs1 dout22/vs0 dout21/hs0 dout20 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 avdd ep ms /hven pclkout dout0 dout1 dout2 dout3 iovdd dout4 dout5 dout6 dout7 dvdd tx /scl / es rx/sda /edc gpi in- in+ avdd lccen i2csel cx / tp gpio0/dbl gpi01/ bws 36 35 34 33 32 31 30 29 28 27 26 25 dout19 dout18 dout17 dout16 dout15 dout14 dout13 dout12 dout11 dout10 dout9 dout8 MAX9240A MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 13 pin coniguration downloaded from: http:///
pin name function 1 gpio1/bws gpio/bus width select input. function is determined by the state of lccen (table 12). gpio1 (lccen = high): open-drain, general-purpose input/output with internal 60k? pullup to iovdd. bws (lccen = low): input with internal pulldown to ep. set bws = low for 22-bit input latch. set bws = high for 30-bit input latch. 2 gpio0/dbl gpio/double-mode input. function is determined by the state of lccen (table 12). gpio0 (lccen = high): open-drain, general-purpose input/output with internal 60k? pullup to iovdd. dbl (lccen = low): input with internal pulldown to ep. set dbl = high to use double-input mode. set dbl = low to use single-input mode. 3 cx/tp coax/twisted-pair three-level coniguration input (table 7) 4 i2csel i 2 c select. control-channel interface protocol select input with internal pulldown to ep. set i2csel = high to select i 2 c slave interface. set i2csel = low to select uart interface. 5 lccen local control-channel enable input with internal pulldown to ep. lccen = high enables the control- channel interface pins. lccen = low disables the control-channel interface pins and selects an alternate function on the indicated pins (table 12). 6, 48 avdd 1.8v analog power supply. bypass avdd to ep with 0.1f and 0.001f capacitors as close as possible to the device with the smaller capacitor closest to avdd. 7 in+ noninverting coax/twisted-pair serial input 8 in- inverting coax/twisted-pair serial input 9 gpi general-purpose input. the gmsl serializer gpo (or int) input follows gpi. 10 rx/sda/edc receive/serial data/error detection correction. function is determined by the state of lccen (table 12). rx/sda (lccen = high): input/output with internal 30k? pullup to iovdd. in uart mode, rx/sda is the rx input of the MAX9240As uart. in the i 2 c mode, rx/sda is the sda input/output of the MAX9240As i 2 c master/slave. rx/sda has an open-drain driver and requires a pullup resistor. edc (lccen = low): input with internal pulldown to ep. set edc = high to enable error detection correction. set edc = low to disable error detection correction. 11 tx/scl/es transmit/serial clock/edge select. function is determined by the state of lccen (table 12). tx/scl (lccen = high): input/output with internal 30k? pullup to iovdd. in uart mode, tx/scl is the tx output of the MAX9240As uart. in the i 2 c mode, tx/scl is the scl input/output of the MAX9240As i 2 c master/slave. tx/scl has an open-drain driver and requires a pullup resistor. es (lccen = low): input with internal pulldown to ep. when es is high, pclkout indicates valid data on the falling edge of pclkout. when es is low, pclkout indicates valid data on the rising edge of pclkout. do not change the es input while the pixel clock is running. 12 dvdd 1.8v digital power supply. bypass dvdd to ep with 0.1f and 0.001f capacitors as close as possible to the device with the smaller value capacitor closest to dvdd. 13 pwdn active-low power-down input with internal pulldown to ep. set pwdn low to enter power-down mode to reduce power consumption. 14 err error output. open-drain data error detection and/or correction indication output with internal 60k? pullup to iovdd. err is output high when pwdn = low. MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 14 pin description downloaded from: http:///
pin name function 15 lock open-drain lock output with internal 60k? pullup to iovdd. lock = high indicates that plls are locked with correct serial-word-boundary alignment. lock = low indicates that plls are not locked or an incorrect serial-word-boundary alignment. lock remains low when the coniguration link is active o r during prbs test. lock is output high when pwdn = low. 16 lmn0 line fault monitor input 0 (figure 4) 17 lmn1 line fault monitor input 1 (figure 4) 18 lflt active-low open-drain line fault output. lflt has a 60k? internal pullup to iovdd. lflt = low indicates a line fault. lflt is output high when pwdn = low. 19 dout24/vs1 parallel data/vertical sync 1 output. defaults to parallel data output on power-up. parallel data output when vs/hs encoding is disabled. decoded vertical sync for upper half of single-output when vs/hs encoding is enabled (table 1). 20, 41 iovdd i/o supply voltage. 1.8v to 3.3v logic i/o power supply. bypass iovdd to ep with 0.1f and 0.001f capacitors as close as possible to the device with the smallest value capacitor closest to iovdd. 21 dout23/hs1 parallel data/horizontal sync 1 output. defaults to parallel data output on power-up. parallel data output when vs/hs encoding is disabled. decoded horizontal sync for upper half of single-output when vs/hs encoding is enabled (table 1). 22 dout22/vs0 parallel data/vertical sync 0 output. defaults to parallel data output on power-up. parallel data output when vs/hs encoding is disabled. decoded vertical sync for lower half of single-output when vs/hs encoding is enabled (table 1). 23 dout21/hs0 parallel data/horizontal sync 0 output. defaults to parallel data output on power-up. parallel data output when vs/hs encoding is disabled. decoded horizontal sync for lower half of single-output when vs/hs encoding is enabled (table 1). 24C40, 42C45 dout20C dout0 parallel data outputs 46 pclkout parallel clock output. latches parallel data into the input of another device. 47 ms/hven mode select/hs and vs encoding enable with internal pulldown to ep. function is determined by the state of lccen (table 12). ms (lccen = high): set ms = low to select base mode. set ms = high to select the bypass mode.hven (lccen = low): set hven = high to enable hs/vs encoding on dout_/hs_ and dout_/vs_. set hven = low to use dout_/hs_ and dout_/vs_ as parallel data outputs. ep exposed pad. ep is internally connected to device ground. must connect ep to the pcb ground plane through an array of vias for proper thermal and electrical performance. MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 15 pin description (continued) downloaded from: http:///
fcc dout[20:0] pclkout dout21/hs0 dout22/ vs0 dout23/hs1 dout24/ vs1 gpio vs / hs gpio1/bws sspll clkdiv cdrpll cml rx and eq gpi gpio0 /dbl scramble/ crc/ hamming/ 8b/10b decode reverse control channel serial to parallel tx/scl/es rx/sda/edc uart/i 2 c t x in+in- fifo 1x[24:0] or 2x[10:0] or 2x[14:0] line fault lmn0lmn1 lflt MAX9240A MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 16 functional diagram downloaded from: http:///
figure 1. reverse control-channel output parameters reverse control-channel transmitter in+ in- in- in+ in+ in- v od r l /2 r l /2 v cmr v cmr v roh (in+) - (in-) t r 0.1 x v rol 0.9 x v rol t f v rol 0.9 x v roh 0.1 x v roh MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 17 downloaded from: http:///
figure 2. test circuit for differential input measurement figure 4. line fault figure 3. test circuit for single-ended input measurement v in+ r l /2 r l /2 c in c in v id(p) in+ in- v id(p) = | v in+ - v in- | v cmr = (v in+ + v in- )/2 v in- _ + _ _ + output logic (in+) output logic (in-) reference voltage generator gmsl deserializer gmsl deserializer twisted pair connectors *1% tolerance lflt lmn0 1.8v lmn1 49.9k ? * 49.9k ? * lmn1in+ in- 4.99k ? * 45.3k ? * 45.3k ? * 4.99k ? * lmn0 gmsl deserializer coax connectors 1.8v 49.9k ? * in+in- 45.3k ? * lmn0 4.99k ?* 49.9 ? * c in 0.22 f 49.9 ? + - v in_ in_ v is(p) MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 18 downloaded from: http:///
figure 5. worst-case pattern output figure 6. parallel clock output high and low times figure 7. i 2 c timing parameters pclkout dout_ note: pclkout programmed for rising latch edge. v ol max t high t low t t v oh min pclkout protocol scl sda start condition (s) bit 7 msb (a7) bit 6 (a6) bit 0 (r/w) acknowledge (a) stop condition (p) v iovdd x 0.7 v iovdd x 0.3 v iovdd x 0.7 v iovdd x 0.3 t su;sta t low t high t buf t hd;sta t r t sp t f t su;dat t hd;dat t vd;dat t vd;ack t su;sto 1/f scl MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 19 downloaded from: http:///
figure 8. output rise-and-fall times figure 10. gpi-to-gpo delay figure 9. deserializer delay 0.8 x v i0vdd 0.2 x v i0vdd t f t r c l single-ended output load t gpio t gpio v oh_min v ol_max v ih_min v il_max deserializer gpi serializer gpo first bit in+/- dout_ pclkout last bit serial word n serial-word length serial word n+1 serial word n+2 t sd parallel word n-2 parallel word n-1 parallel word n note: pclkout programmed for rising latching edge. MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 20 downloaded from: http:///
detailed description the MAX9240A deserializer, when paired with the max9271 or max9273 serializer, provides the full set of operating features, but offers basic functionality when paired with any gmsl serializer. the deserializer has a maximum serial-bit rate of 1.5gbps for 15m or more of cable and operates up to a maximum output clock of 50mhz in 25-bit, single-output mode, or 75mhz to 100mhz in 15-bit/11-bit, double-output mode, respectively. this bit rate and output flexibility support a wide range of displays, from qvga (320 x 240) to wvga (800 x 480) and higher with 18-bit color, as well as megapixel image sensors. input equalization, combined with gmsl serializer pre/deemphasis, extends the cable length and enhances link reliability the control channel enables a c to program the serial - izer and deserializer registers and program registers on peripherals. the control channel is also used to configure and access the gpio. the c can be located at either end of the link, or when using two cs, at both ends. two modes of control-channel operation are available. base mode uses either i 2 c or gmsl uart protocol, while bypass mode uses a user-defined uart protocol. uart protocol allows full-duplex communication, while i 2 c allows half-duplex communication. spread spectrum is available to reduce emi on the paral - lel output. the serial input complies with iso 10605 and iec 61000-4-2 esd protection standards. register mapping registers set the operating conditions of the deserializer and are programmed using the control channel in base mode. the deserializer holds its device address and the device address of the serializer it is paired with. similarly, the serializer holds its device address and the address of the deserializer. whenever a device address is changed, the new address should be written to both devices. the default device address of the deserializer is set by the cx/tp input and the default device address of any gmsl serializer is 0x80 (see table 7 ). registers 0x00 and 0x01 in both devices hold the device addresses.bit map the parallel output functioning and width depend on settings of the double-/single-output mode (dbl), hs/vs encoding (hven), error correction used (edc), and bus width (bws) pins. table 1 lists the bit map for the control pin settings. unused output bits are pulled low. the parallel output has two output modes: single and double output. in single-output mode, the deserialized parallel data is clocked out every pclkout cycle. the device accepts pixel clocks from 6.25mhz to 50mhz ( figure 13 and figure 14 ). in double-output mode, the device splits deserialized data into two half-sized words that are output at twice the serial-word rate ( figure 15 and figure 16 . the serializer/deserializer use pixel clock rates from 33.3mhz to 100mhz for 11-bit, double-output mode and 25mhz to 75mhz for 15-bit, double-output mode. figure 11. lock time figure 12. power-up delay in+ - in-lock t lock pwdn must be high v oh in+/- lock t pu pwdn v oh v ih1 MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 21 downloaded from: http:///
figure 13. single-output waveform (serializer using single input) figure 14. single-output waveform (serializer using double input) pclkout vs0, vs1 hs0, hs1 dout[24:0] or dout[21:0] first word second word third word fourth word vs (from first word) vs (from second word) vs (from third word) vs (from fourth word) hs (from first word) hs (from second word) hs (from third word) hs (from fourth word) note: diagram shows possible locations for transitions on vs_ /hs_. vs_ /hs_ have minimum length requirements. note: hs_, vs_ active only when hven = 1. pclkout vs0, hs0 dout[14:0] or dout[10:0] first word (from latch a) second word (from latch a) third word (from latch a) fourth word (from latch a) first word (from latch b) second word (from latch b) third word (from latch b) fourth word (from latch b) first word (from latch a) second word (from latch a) third word (from latch a) fourth word (from latch a) vs1, hs1 first word (from latch b) second word (from latch b) third word (from latch b) fourth word (from latch b) note: diagram shows possible locations for transitions on vs_ /hs_. vs_ /hs_ have minimum length requirements. note: hs_, vs_ active only when hven = 1. dout[24:15] or dout[21:11] MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 22 downloaded from: http:///
figure 15. double-output waveform (serializer using single input) figure 16. double-output waveform (serializer using double input) pclkout vs0, hs0 (serializer dbl = 0) dout[14:0] or dout[10:0] douta first word doutb first word douta second word doutb second word second word first word note: diagram shows possible locations for transitions on vs0 /hs0. vs0 /hs0 have minimum length requirements. note: hs0, vs0 active only when hven = 1. pclkout vs0, hs0 (serializer dbl = 1) dout[14:0] or dout[10:0] douta first word doutb first word douta second word doutb second word douta first word doutb first word douta second word doutb second word note: diagram shows possible locations for transitions on vs0 /hs0. vs0 /hs0 have minimum length requirements. note: hs0, vs0 active only when hven = 1. MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 23 downloaded from: http:///
table 1. output map * the number of available outputs depends on the serializer attached to the MAX9240A. ** device is in high-speed mode (drs = low). see table 2 for pclk ranges in low-speed mode (drs = high). edc bws dbl hven output* (paired with max9271) output* (paired with max9273) pclk range** (mhz) 00 0 0 0 dout0:15 dout0:21 16.66 to 50 00 0 0 1 dout0:13, hs, vs dout0:20, hs, vs 16.66 to 50 00 0 1 0 dout0:10 dout0:10 33.33 to 100 00 0 1 1 dout0:10, hs, vs dout0:10, hs, vs 33.33 to 100 00 1 0 0 dout0:15 dout0:21 12.5 to 37.5 00 1 0 1 dout0:13, hs, vs dout0:20, hs, vs 12.5 to 37.5 00 1 1 0 dout0:14 dout0:14 25 to 75 00 1 1 1 dout0:13, hs, vs dout0:14, hs, vs 25 to 75 01, 10 0 0 0 dout0:15 dout0:15 16.66 to 50 01, 10 0 0 1 dout0:13, hs, vs dout0:15, hs, vs 16.66 to 50 01, 10 0 1 0 dout0:7 dout0:7 33.33 to 100 01, 10 0 1 1 dout0:7, hs, vs dout0:7, hs, vs 33.33 to 100 01, 10 1 0 0 dout0:15 dout0:21 12.5 to 37.5 01, 10 1 0 1 dout0:13, hs, vs dout0:20, hs, vs 12.5 to 37.5 01, 10 1 1 0 dout0:11 dout0:11 25 to 75 01, 10 1 1 1 dout0:11, hs, vs dout0:11, hs, vs 25 to 75 MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 24 downloaded from: http:///
serial link signaling and data format the serializer uses differential cml signaling to drive twist - ed-pair cable and single-ended cml to drive coax cable with programmable pre/deemphasis and ac-coupling. the deserializer uses ac-coupling and programmable channel equalization. input data is scrambled and then 8b/10b coded. the deserializer recovers the embedded serial clock, then samples, decodes, and descrambles the data. in 24-bit or 32-bit mode, 22 or 30 bits contain the video data and/or error-correction bits, if used. the 23rd or 31st bit carries the forward control-channel data. the last bit is the parity bit of the previous 23 or 31 bits ( figure 17 ). reverse control channel the serializer uses the reverse control channel to receive i 2 c/uart and gpo signals from the deserializer in the opposite direction of the video stream. the reverse control channel and forward video data coexist on the same serial cable, forming a bidirectional link. the reverse control channel operates independently from the forward control channel. the reverse control channel is available 2ms after power-up. the serializer temporarily disables the reverse control channel for 350s after start - ing/stopping the forward serial link. data-rate selection the serializer/deserializer use drs, dbl, and bws to set the pclkout frequency range ( table 2 ). set drs = 1 for a pclkout frequency range of 6.25mhz to 12.5mhz (32-bit, single-output mode) or 8.33mhz to 16.66mhz (24- bit, single-output mode). set drs = 0 for normal opera - tion. it is not recommended to use double-output mode when drs = 1. table 2. data-rate selection table figure 17. serial-data format drs setting dbl setting bws setting pclkout range (mhz) 0 0 (single input) 0 (24-bit mode) 16.66 to 50 0 0 1 (32-bit mode) 12.5 to 35 0 1 (double input) 0 33.3 to 100 0 1 1 25 to 75 1 0 0 8.33 to 16.66 1 0 1 6.25 to 12.5 1 1 0 do not use 1 1 1 do not use d0 d1 d21 fcc pcb d0 d1 d29 fcc pcb forward control- channel bit packet parity check bit note: serial data shown before scrambling and 8b/10b encoding video and error correction data 24 bits 32 bits forward control- channel bit packet parity check bit video and error correction data MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 25 downloaded from: http:///
control channel and register programming the control channel is available for the c to send and receive control data over the serial link simultaneously with the high-speed data. the c controls the link from either the serializer or the deserializer side to support video-display or image-sensing applications. the control channel between the c and serializer or deserializer runs in base mode or bypass mode, according to the mode selection (ms/hven) input of the device connected to the c. base mode is a half-duplex control channel and bypass mode is a full-duplex control channel. uart interface in base mode, the c is the host and can access the registers of both the serializer and deserializer from either side of the link using the gmsl uart protocol. the c can also program the peripherals on the remote side by sending the uart packets to the serializer or deserializer, with the uart packets converted to i 2 c by the device on the remote side of the link. the c communicates with a uart peripheral in base mode (through inttype register settings), using the half- duplex default gmsl uart protocol of the serializer/ deserializer. the device addresses of the serializer/ deserializer in base mode are programmable. the default value is 0x80 for the serializer and is determined by the cx/tp input for the deserializer ( table 7 ). when the peripheral interface is i 2 c, the serializer/ deserializer convert uart packets to i 2 c that have device addresses different from those of the serializer or deserializer. the converted i 2 c bit rate is the same as the original uart bit rate. the deserializer uses differential line coding to send signals over the reverse channel to the serializer. the bit rate of the control channel is 9.6kbps to 1mbps in both directions. the serializer/deserializer automatically detect the control-channel bit rate in base mode. packet bit-rate changes can be made in steps of up to 3.5 times higher or lower than the previous bit rate. see the changing the clock frequency section for more information. figure 18 shows the uart protocol for writing and read - ing in base mode between the c and the serializer/ deserializer. figure 19 shows the uart data format. even parity is used. figure 20 and figure 21 detail the formats of the sync byte (0x79) and the ack byte (0xc3). the c and the con - nected slave chip generate the sync byte and ack byte, respectively. events such as device wake-up and gpi generate transitions on the control channel that can be ignored by the c. data written to the serializer/deserial - izer registers do not take effect until after the ack byte is sent. this allows the c to verify that write commands are received without error, even if the result of the write com - mand directly affects the serial link. the slave uses the sync byte to synchronize with the host uarts data rate. if the gpi or ms/hven inputs of the deserializer toggle while there is control-channel communication, or if a line fault occurs, the control-channel communication is cor - rupted. in the event of a missed or delayed acknowledge (~1ms due to control-channel timeout), the c should assume there was an error in the packet transmission or response. in base mode, the c must keep the uart tx/ rx lines high no more than 4 bit times between bytes in a packet. keep the uart tx/rx lines high for at least 16 bit times before starting to send a new packet. figure 18. gmsl uart protocol for base mode write data format sync dev addr + r/ w reg addr number of bytes sync dev addr + r/ w reg addr number of bytes byte 1 byte n ack byte n byte 1 ack master reads from slave read data format master writes to slave master writes to slave master reads from slave MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 26 downloaded from: http:///
as shown in figure 22 , the remote-side device converts packets going to or coming from the peripherals from uart format to i 2 c format and vice versa. the remote device removes the byte number count and adds or receives the ack between the data bytes of i 2 c. the i 2 c bit rate is the same as the uart bit rate. interfacing command-byte-only i 2 c devices with uart the serializer/deserializer uart-to-i 2 c conversion can interface with devices that do not require register addresses, such as the max7324 gpio expander. in this mode, the i 2 c master ignores the register address byte and directly reads/writes the subsequent data bytes ( figure 23 ). change the communication method of the i 2 c master using the i2cmethod bit. i2cmethod = 1 sets command-byte-only mode, while i2cmethod = 0 sets normal mode where the first byte in the data stream is the register address. uart bypass mode in bypass mode, the serializer/deserializer ignore uart commands from the c and the c communicates with the peripherals directly using its own defined uart pro - tocol. the c cannot access the serializer/deserializer registers in this mode. peripherals accessed through the forward control channel using the uart interface need to handle at least one pclkout period 10ns of jitter due to the asynchronous sampling of the uart signal by pclkout. set ms/hven = high to put the control channel into bypass mode. for applications with the c connected to the deserializer, there is a 1ms wait time between setting ms/hven high and the bypass con - trol channel being active. there is no delay time when switching to bypass mode when the c is connected to the serializer. do not send a logic-low value longer than 100s to ensure proper gpo functionality. bypass mode accepts bit rates down to 10kbps in either direction. see the gpo/gpi control section for gpi functionality limita - tions. the control-channel data pattern should not be held low longer than 100s if gpi control is used. i 2 c interface in i 2 c-to-i 2 c mode, the deserializers control-channel interface sends and receives data through an i 2 c- compatible 2-wire interface. the interface uses a serial- data line (sda) and a serial-clock line (scl) to achieve bidirectional communication between master and slave(s). a c master initiates all data transfers to and from the device and generates the scl clock that synchronizes the data transfer. when an i 2 c transaction starts on the local-side devices control-channel port, the remote-side devices control-channel port becomes an i 2 c master that interfaces with remote-side i 2 c perhipherals. the i 2 c master must accept clock stretching, which is imposed by the deserializer (holding scl low). the sda and scl lines operate as both an input and an open-drain output. pullup resistors are required on sda and scl. each transmis - sion consists of a start condition ( figure 7 ) sent by a master, followed by the devices 7-bit slave address plus a r/ w bit, a register address byte, one or more data bytes, and finally a stop condition. figure 19. gmsl uart data format for base mode figure 20. sync byte (0x79) figure 21. ack byte (0xc3) start *base mode uses even parity d0 d1 d2 d3 d4 d5 d6 d7 parity stop 1 uart frame frame 1 frame 2 frame 3 stop start stop start start d0 1 0 0 1 1 1 1 0 d1 d2 d3 d4 d5 d6 d7 parity stop start d0 1 1 0 0 0 0 1 1 d1 d2 d3 d4 d5 d6 d7 parity stop MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 27 downloaded from: http:///
figure 22. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 0) figure 23. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 1) 11 sync frame register address number of bytes device id + wr data 0 dev id a 11 11 11 11 data n 11 11 s 1 1 1 ack frame 7 : master to slave 8 serializer/deserializer peripheral w 1 reg addr 8 a 1 1 8 1 11 sync frame register address number of bytes device id + rd 11 11 11 11 ack frame data 0 11 data n 11 uart-to-i 2 c conversion of write packet (i2cmethod = 0) uart-to-i 2 c conversion of read packet (i2cmethod = 0) s: start p: stop a: acknowledge : slave to master data 0 a data n a p dev id a s 1 1 7 w 1 dev id a s 1 1 7 r 1 data n p 1 8 a 1 data 0 8 a 1 reg addr 8 a 1 c serializer/deserializer c serializer/deserializer serializer/deserializer peripheral : master to slave serializer/deserializer serializer/deserializer serializer/deserializer uart-to-i 2 c conversion of read packet (i2cmethod = 1) uart-to-i 2 c conversion of write packet (i2cmethod = 1) c serializer/deserializer c sync frame 11 11 11 11 11 11 11 11 11 11 11 11 11 11 device id + rd register address number of bytes sync frame device id + wr register address number of bytes data 0 data n ack frame ack frame data 0 data n data n a data 0 w a dev id s a p peripheralperipheral s 1 1 1 8 8 8 1 11 1 7 1 1 8 1 1 1 7 dev id r a a a p data 0 data n : slave to master s: start p: stop a: acknowledge MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 28 downloaded from: http:///
start and stop conditions both scl and sda remain high when the interface is not busy. a master signals the beginning of a transmission with a start (s) condition by transitioning sda from high to low while scl is high ( figure 24 ). when the master has finished communicating with the slave, it issues a stop (p) condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission. bit transfer one data bit is transferred during each clock pulse ( figure 25 ). the data on sda must remain stable while scl is high. acknowledge the acknowledge bit is a clocked 9th bit that the recipi - ent uses to handshake receipt of each byte of data ( figure 26 ). thus, each byte transferred effectively requires 9 bits. the master generates the 9th clock pulse, and the recipient pulls down sda during the acknowledge clock pulse. the sda line is stable low during the high period of the clock pulse. when the master is transmitting to the slave device, the slave device generates the acknowl - edge bit because the slave device is the recipient. when the slave device is transmitting to the master, the master generates the acknowledge bit because the master is the recipient. the device generates an acknowledge even when the forward control channel is not active (not locked). to prevent acknowledge generation when the forward control channel is not active, set the i2clocack bit low. figure 24. start and stop conditions figure 25. bit transfer figure 26. acknowledge sda scl start condition stop condition s p sda scl data line stable; data valid change of data allowed scl sda by transmitter clock pulse for acknowledge start condition sda by receiver 1 2 8 9 s MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 29 downloaded from: http:///
slave address the serializer/deserializer have a 7-bit-long slave address. the bit following a 7-bit slave address is the r/ w bit, which is low for a write command and high for a read command. the slave address is 100100x1 for read commands and 100100x0 for write commands. see figure 27 . bus reset the device resets the bus with the i 2 c start condition for reads. when the r/ w bit is set to 1, the serializer/ deserializer transmit data to the master, thus the master is reading from the device. format for writing a write to the serializer/deserializer comprises the trans - mission of the slave address with the r/ w bit set to zero, followed by at least one byte of information. the first byte of information is the register address or command byte. the register address determines which register of the device is to be written by the next byte, if received. if a stop (p) condition is detected after the register address is received, the device takes no further action beyond storing the register address ( figure 28 ). any bytes received after the register address are data bytes. the first data byte goes into the register selected by the register address, and subsequent data bytes go into subsequent registers ( figure 29 ). if multiple data bytes are transmitted before a stop condition, these bytes are stored in subsequent registers because the register addresses autoincrement. format for reading the serializer/deserializer are read using the internally stored register address as an address pointer, the same way the stored register address is used as an address pointer for a write. the pointer autoincrements after each data byte is read using the same rules as for a write. thus, a read is initiated by first configuring the register address by performing a write ( figure 30 ). the master can now read consecutive bytes from the device, with the first data byte being read from the register address pointed by the previously written register address. once the master sends a nack, the device stops sending valid data. figure 27. slave address figure 28. format for i 2 c write figure 29. format for write to multiple registers sda 0 ack scl msb lsb 1 0 r/ w 0 1 0 1/0 s 1 0 0 0 address = 0x80 0 = write 0 0 0 0 a 0 0 0 0 register address = 0x00 0 0 0 0 a p d7 d6 d5 d4 register 0x00 write data d3 d2 d1 d0 a s = start bit p = stop bit a = ack d_ = data bi t s = start bit p = stop bit a = ack n = nack d_ = data bi t s 1 0 0 0 address = 0x80 0 = write 0 0 0 0 a 0 0 0 0 register address = 0x0000 0 0 0 0 a d7 d6 d5 d4 register 0x00 write data d3 d2 d1 d0 a d7 p d6 d5 d4 register 0x02 write data d3 d2 d1 d0 n MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 30 downloaded from: http:///
i 2 c communication with remote-side devices the deserializer supports i 2 c communication with a peripheral on the remote side of the communication link using scl clock stretching. while multiple masters can reside on either side of the communication link, arbitra - tion is not provided. the connected masters need to sup - port scl clock stretching. the remote-side i 2 c bit-rate range must be set according to the local-side i 2 c bit rate. supported remote-side bit rates can be found in table 3 . set the i2cmstbt (register 0x0d) to set the remote i 2 c bit rate. if using a bit rate different than 400kbps, local- and remote-side i 2 c setup and hold times should be adjusted by setting the slv_sh register settings on both sides. i 2 c address translation the deserializer supports i 2 c address translation for up to two device addresses. use address translation to assign unique device addresses to peripherals with limited i 2 c addresses. source addresses (address to translate from) are stored in registers 0x09 and 0x0b. destination addresses (address to translate to) are stored in registers 0x0a and 0x0c. control-channel broadcast mode the deserializer supports broadcast commands to con - trol multiple peripheral devices. select an unused device address to use as a broadcast device address. program the remote-side gmsl device to translate the broadcast device address (source address stored in registers 0x09, 0x0b) to the peripheral device address (destination address stored in registers 0x0a, 0x0c). any commands sent to the broadcast address are sent to all designated peripherals, while commands sent to a peripherals unique device address are sent to that particular device only. gpo/gpi control gpo on the serializer follows gpi transitions on the deserializer. this gpo/gpi function can be used to transmit signals such as frame sync in a surround- view camera system. the gpi-to-gpo delay is 0.35ms (max). keep the time between gpi transitions to a minimun 0.35ms. this includes transitions from the other deserializer in coax-splitter mode. bit d4 of register 0x0e in the deserializer stores the gpi input state. gpo is low after power-up. the c can set gpo by writing to the serializer set_gpo register bit. do not send a logic-low value on the deserializer rx/sda input (uart mode) longer than 100s in either base or bypass mode to ensure proper gpo/gpi functionality. figure 30. format for i 2 c read table 3. i 2 c bit-rate ranges local bit rate remote bit-rate range i2cmstbt setting f > 50kbps up to 1mbps any 20kbps < f < 50kbps up to 400kbps up to 110 f < 20kbps up to 10kbps 000 s = start bit p = stop bit a = ack n = nack d_ = data bi t s s 1 0 0 0 address = 0x80 0 = write 0 0 0 0 a 1 = read repeated start 0 0 0 0 register address = 0x00 0 0 0 0 a 1 0 0 0 address = 0x81 0 0 0 0 a d7 p d6 d5 d4 register 0x00 read data d3 d2 d1 d0 n MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 31 downloaded from: http:///
prbs test the serializer includes a prbs pattern generator that works with bit-error verification in the deserializer. to run the prbs test, set prbsen = 1 (0x04, d5) in the deseri - alizer and then in the serializer. to exit the prbs test, set prbsen = 0 (0x04, d5) in the serializer. line equalizer the deserializer includes an adjustable line equalizer to further compensate cable attenuation at high frequencies. the cable equalizer has 11 selectable levels of compen - sation from 2.1db to 13db ( table 4 ). the device powers up with the equalizer disabled. to select other equaliza - tion levels, set the corresponding register bits in the dese - rializer (0x05 d[3:0]). use equalization in the deserializer, together with preemphasis in the serializer, to create the most reliable link for a given cable. spread spectrum to reduce the emi generated by transitions, the dese - rializer output is programmable for spread spectrum. if the serializer driving the deserializer has programmable spread spectrum, do not enable spread for both at the same time or their interaction will cancel benefits. the programmable spread-spectrum amplitudes are 2% and 4% ( table 5 ). the deserializer includes a sawtooth divider to control the spread-modulation rate. autodetection of the pclkout operation range guarantees a spread- spectrum modulation frequency within 20khz to 40khz. additionally, manual configuration of the sawtooth divider (sdiv: 0x03, d[5:0]) allows the user to set a modulation frequency according to the pclkout frequency. when ranges are manually selected, program the sdiv value for a fixed modulation frequency around 20khz. manual programming of the spread-spectrum divider the modulation rate for the deserializer relates to the pclkout frequency as follows: ( ) pclkout m f f 1 drs mod sdiv = + where:f m = modulation frequency drs = drs value (0 or 1) f pclkout = pclkout frequency mod = modulation coefficient given in table 6 sdiv = 5-bit sdiv setting, manually programmed by the c to program the sdiv setting, first look up the modulation coefficient according to the desired bus-width and spread- spectrum settings. solve the above equation for sdiv using the desired pixel clock and modulation frequencies. if the calculated sdiv value is larger than the maximum allowed sdiv value in table 6 , set sdiv to the maximum value. table 4. cable equalizer boost levels table 5. parallel output spread table 6. modulation coefficients and maximum sdiv settings boost setting (0x05 d[3:0]) typical boost gain (db) 0000 2.1 0001 2.8 0010 3.4 0011 4.2 0100 5.2 0101 6.2 0110 7 0111 8.2 1000 9.4 1001 10.7 default* 1010 11.7 1011 13 ss spread (%) 00 no spread spectrum. power-up default. 01 2% spread spectrum. 10 no spread spectrum. 11 4% spread spectrum. spread- spectrum setting (%) modulation coefficient (dec) sdiv upper limit (dec) 4 208 15 2 208 30 MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 32 downloaded from: http:///
additional error detection and correction in default mode (additional error detection and correction disabled), data encoding/decoding is the same as in previous gmsl serializers/deserializers (parity only). at the serializer, the parallel input word is scrambled and a parity bit is added. the scrambled word is divided into 3 or 4 bytes (depending on the bws setting), 8b/10b encoded, and then transmitted serially. at the deserializer, the same operations are performed in reverse order. the parity bit is used by the deserializer to find the word boundary and for error detection. errors are counted in an error counter register and an error pin indicates errors. the deserializer can use one of two additional error-detection/ correction methods (selectable by register setting): 1) 6-bit cyclic redundancy check 2) 6-bit hamming code with 16-word interleaving cyclic redundancy check (crc) when crc is enabled, the serializer adds 6 bits of crc to the input data. this reduces the available bits in the input data word by 6, compared to the non-crc case (see table 1 for details). for example, 16 bits are avail - able for input data instead of 22 bits when bws = 0, and 24 bits instead of 30 bits when bws = 1. the crc generator polynomial is x 6 + x + 1 (as used in the itu-t g704 telecommunication standard). the parity bit is still added when crc is enabled, because it is used for word-boundary detection. when crc is enabled, each data word is scrambled and then the 6-bit crc and 1-bit parity are added before the 8b/10b encoding. at the deserializer, the crc code is recalculated. if the recalculated crc code does not match the received crc code, an error is flagged. this crc error is reported to the error counter. hamming code hamming code is a simple and effective error-correction code to detect and/or correct errors. the MAX9240A deserializer (when used with the max9271/max9273 gmsl serializers) uses a single-error correction/double- error detection per pixel hamming-code scheme. the deserializer uses data interleaving for burst error tolerance. burst errors up to 11 consecutive bits on the serial link are corrected and burst errors up to 31 consecutive bits are detected. hamming code adds overhead similar to crc. see table 1 for details regarding the available input word size. hs/vs encoding and/or tracking hs/vs encoding by a gmsl serializer allows horizontal and vertical synchronization signals to be transmitted while conserving pixel data bandwidth. with hs/vs encod - ing enabled, 10-bit pixel data with a clock up to 100mhz can be transmitted using one video pixel of data per hs/ vs transition vs. 8-bit data with a clock up to 100mhz without hs/vs encoding. the deserializer performs hs/ vs decoding, tracks the period of the hs/vs signals, and uses voting to filter hs/vs bit errors. when using hs/vs encoding, use a minimum hs/vs low-pulse duration of two pclkout cycles when dbl = 0 on the deserializer. when dbl = 1, use a minimum hs/vs low-pulse duration of five pclkout cycles and a minimum high-pulse duration of two pclkout cycles. when using hamming code with hs/vs encoding, do not send more than two transitions every 16 pclkout cycles. when the serializer uses double-input mode (dbl = 1), the active duration, plus the blanking duration of hs or vs signals, should be an even number of pclkout cycles. when dbl = 1 in the serializer and dbl = 0 in the deserializer, two pixel clock cycles of hs/vs at the serial - izer input are output at the hs0/vs0 and hs1/vs1 output of the deserializer in one cycle. the first cycle of hs/vs goes out of hs0/vs0 and the second cycle goes out of hs1/vs1. hs1 and vs1 are not used when hven = 0. if hs/vs tracking is used without hs/vs encoding, use dout0 for hsync and dout1 for vsync. in this case, if dbl values on the serializer/deserializer are different, set the uneqdbl register bit in the deserializer to 1. if the serializer and deserializer have unequal dbl settings and hven = 0, then hs/vs inversion should only be used on the side that has dbl = 1. hs/vs encoding sends packets when hsync or vsync is low; use hs/ vs inversion register bits if input hsync and vsync signals use an active-low convention in order to send data packets during the inactive pixel clock periods. serial input the device can receive serial data from two kinds of cables: 100 twisted pair and 50 coax (contact the factory for devices compatible with 75 cables). coax-mode splitter in coax mode, out+ and out- of the serializer are active. this enables use as a 1:2 splitter ( figure 31 ). in coax mode, connect out+ to in+ of the deserializer. connect out- to in- of the second deserializer. control-channel data is broadcast from the serializer to both deserializers and their attached peripherals. assign a unique address MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 33 downloaded from: http:///
to send control data to one deserializer. leave all unused in_ pins unconnected, or connect them to ground through 50 and a capacitor for increased power-supply rejection. if out- is not used, connect out- to avdd through a 50 resistor ( figure 32 ). when there are cs at the serializer, and at each deserializer, only one c can communicate at a time. disable one splitter control-channel link to prevent contention. use the dis_rev_p or dis_rev_n register bits to disable a control-channel link. cable type coniguration input (cx/tp) cx/tp determines the power-up state of the serial input. in coax mode, cx/tp also determines which coax input is active, along with the default device address ( table 7 ). these functions can be changed after power-up by writing to the appropriate register bits. sleep mode the deserializer includes a sleep mode to reduce power consumption. the device enters or exits sleep mode by a command from a local c or a remote c using the con - trol channel. set the sleep bit to 1 to initiate sleep mode. the serializer sleeps immediately after setting its sleep = 1. the deserializer sleeps after serial link inactivity or 8ms (whichever arrives first) after setting its sleep = 1. to wake up from the local side, send an arbitrary control- channel command to the deserializer, wait 5ms for the chip to power up, and then write 0 to the sleep register bit to make the wake-up permanent. to wake up from the remote side, enable serialization. to deserializer detects the activity on the serial link and then when it locks, it automatically sets its sleep register bit to 0. power-down mode the deserializer has a power-down mode that further reduces power consumption compared to sleep mode. set pwdn low to enter power-down mode. in power- down mode, the outputs of the device remain in high impedance. entering power-down resets the devices registers. upon exiting power-down, the state of external pins gpio1/bws, gpio0/dbl, cx/tp, i2csel, lccen, rx/sda/edc, tx/scl/es, and ms/hven are latched. coniguration link the control channel can operate in a low-speed mode called configuration link in the absence of a clock input. this allows a microprocessor to program configuration registers before starting the video link. an internal oscil - lator provides the clock for the configuration link. set clinken = 1 on the serializer to enable the configuration link. the configuration link is active until the video link is enabled. the video link overrides the configuration link and attempts to lock when seren = 1. figure 31. 2:1 coax-mode splitter connection diagram figure 32. coax-mode connection diagram table 7. configuration input map cx/tp function high coax+ input. device address 0x90. mid coax- input. device address 0x92. low twisted-pair input. device address 0x90. out+ out- optional components for increased power-supply rejection in+in- in+ in- gmsl serializer MAX9240A MAX9240A out+ out- in+ optional components for increased power-supply rejection in- avdd 50 ? gmsl serializer MAX9240A MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 34 downloaded from: http:///
link startup procedure table 8 lists the startup procedure for video-display appli - cations. table 9 lists the startup procedure for image- sensing applications. the control channel is available after the video link or the configuration link is established. if the deserializer powers up after the serializer, the control channel becomes unavailable until 2ms after power-up. table 8. startup procedure for video-display applications no. c serializer deserializer c connected to serializer. sets all coniguration inputs. if any coniguration inputs are available on one end of the link but not on the other, always connects that coniguration input low. sets all coniguration inputs. if any coniguration inputs are available on one end of the link but not on the other, always connects that coniguration input low. 1 powers up. powers up and loads default settings. powers up and loads default settings. 2 enables coniguration link by setting clinken = 1 (if not enabled automatically) and gets an acknowledge. waits for link to be established (~3ms). establishes coniguration link. locks to coniguration link signal. 3 writes one link coniguration bit (drs, bws, or edc) in the deserializer and gets an acknowledge. coniguration changed from default settings (loss-of-lock can occur when bws or edc changes). 4 writes corresponding serializer link coniguration bit and gets an acknowledge. coniguration changed from default settings. relocks to coniguration link signal. 5 waits for link to be established (~3ms) and then repeats steps 3 and 4 until all serial link bits are conigured. 6 writes remaining coniguration bits in the serializer/deserializer and gets an acknowledge. coniguration changed from default settings. coniguration changed from default settings. 7 enables video link by setting seren = 1 and gets an acknowledge. waits for link to be established (~3ms). begins serializing data. locks to serial link signal and begins deserializing data. MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 35 downloaded from: http:///
table 9. startup procedure for image-sensing applications figure 33. state diagram, remote microcontroller application no. c serializer deserializer c connected to deserializer. sets all coniguration inputs. if any coniguration inputs are available on one end of the link but not on the other, always connects that coniguration input low. sets all coniguration inputs. if any coniguration inputs are available on one end of the link but not on the other, always connects that coniguration input low. 1 powers up. powers up and loads default settings. establishes serial link. powers up and loads default settings. locks to serial link signal. 3 writes deserializer coniguration bits and gets an acknowledge. coniguration changed from default settings (loss-of-lock can occur). 4 writes serializer coniguration bits. cannot get an acknowledge (or gets a dummy acknowledge) if loss-of-lock occurred. coniguration changed from default settings. relocks the serial link signal. 5 enables video link by setting seren = 1 (if not enabled automatically). cannot get an acknowledge (or gets a dummy acknowledge) if loss-of-lock occurred. waits for link to be established (~3ms). begins serializing data. locks to serial link signal and begins deserializing data. sleep config link operating program registers power-off high to low sleep = 1, video link or config link not locked after 8ms power-on idle wake-up signal serial port locking signal detected config link unlocked config link locked video link locked video link unlocked 0 sleep 0 sleep all states gpi changes from low to high or pwdn = low or send gpi to gmsl serializer pwdn = high, power-on power-down or power-off serial link activity stops or 8ms elapses after c sets sleep = 1 video link operating prbsen = 0prbsen = 1 video link prbs test MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 36 downloaded from: http:///
applications information error checking the deserializer checks the serial link for errors and stores the number of detected and corrected errors in the 8-bit registers, deterr (0x10) and correrr (0x12). if a large number of 8b/10b errors are detected within a short duration (error rate > 1/4), the deserializer loses lock and stops the error counter. the deserializer then attempts to relock to the serial data. deterr and correrr reset upon successful video link lock, successful readout of their respective registers (through c), or whenever autoerror reset is enabled. the deserializer uses a separate prbs register during the internal prbs test, and deterr and correrr are reset to 0x00. err output the deserializer has an open-drain err output. this output asserts low whenever the number of detected/ corrected errors exceeds their respective error thresholds during normal operation, or when at least one prbs error is detected during prbs test. err deasserts high when - ever deterr and correrr reset, due to deterr/ correrr readout, video link lock, or autoerror reset. autoerror reset the default method to reset errors is to read the respec - tive error registers in the deserializer (0x10, 0x12, and 0x13). autoerror reset clears the error counters deterr/ correrr and the err output ~1s after err goes low. autoerror reset is disabled on power-up. enable autoerror reset through autorst (0x08, d2). autoerror reset does not run when the device is in prbs test mode. dual c control usually systems have one c to run the control channel, located on the serializer side for video-display applica - tions or on the deserializer side for image-sensing appli - cations. however, a c can reside on each side simulta - neously and trade off running the control channel. in this case, each c can communicate with the serializer and deserializer and any peripheral devices. contention occurs if both cs attempt to use the control channel at the same time. it is up to the user to prevent this contention by implementing a higher-level protocol. in addition, the control channel does not provide arbitration between i 2 c masters on both sides of the link. an acknowl - edge frame is not generated when communication fails due to contention. if communication across the serial link is not required, the cs can disable the forward and reverse control channel using the fwdccen and revccen bits (0x04, d[1:0]) in the serializer/deserializer. communication across the serial link is stopped and contention between cs cannot occur. as an example of dual c use in an image-sensing application, the serializer can be in sleep mode and waiting for wake-up by the c on the deserializer side. after wake- up, the serializer-side c assumes master control of the serializers registers. changing the clock frequency it is recommended that the serial link be enabled after the video clock (f pclkout ) and the control-channel clock (f uart /f i2c ) are stable. when changing the clock frequency, stop the video clock for 5s, apply the clock at the new frequency, then restart the serial link or toggle seren. on-the-fly changes in clock frequency are possible if the new frequency is immediately stable and without glitches. the reverse control channel remains unavailable for 350s after serial link start or stop. when using the uart interface, limit on-the-fly changes in f uart to factors of less than 3.5 at a time to ensure that the device recognizes the uart sync pattern. for example, when lowering the uart frequency from 1mbps to 100kbps, first send data at 333kbps then at 100kbps for reduction ratios of 3 and 3.333, respectively. fast detection of loss-of-synchronization a measure of link quality is the recovery time from loss-of- synchronization. the host can be quickly notified of loss- of-lock by connecting the deserializers lock output to the gpi input. if other sources use the gpi input, such as a touch-screen controller, the c can implement a routine to distinguish between interrupts from loss-of-sync and normal interrupts. reverse control-channel communica - tion does not require an active forward link to operate and accurately tracks the lock status of the gmsl link. lock asserts for video link only and not for the configuration link. MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 37 downloaded from: http:///
providing a frame sync (camera applications) the gpi/gpo provides a simple solution for camera applications that require a frame sync signal from the ecu (e.g., surround-view systems). connect the ecu frame sync signal to the gpi input, and connect the gpo output to the camera frame sync input. gpi/gpo have a typical delay of 275s. skew between multiple gpi/ gpo channels is 115s (max). if a lower skew signal is required, connect the cameras frame sync input to one of the gmsl deserializers gpios and use an i 2 c broadcast write command to change the gpio output state. this has a maximum skew of 1.5s. software programming of the device addresses both the serializer and the deserializer have programmable device addresses. this allows multiple gmsl devices, along with i 2 c peripherals, to coexist on the same control channel. the serializer device address is in register 0x00 of each device, while the deserializer device address is in register 0x01 of each device. to change a device address, first write to the device whose address changes (register 0x00 of the serializer for serializer device address change, or register 0x01 of the deserializer for deserializer device address change). then write the same address into the corresponding register on the other device (register 0x00 of the deserializer for serializer device address change, or register 0x01 of the serializer for deserializer device address change). three-level coniguration inputs cx/tp is a three-level input that controls the serial- interface configuration and power-up defaults. connect cx/tp through a pullup resistor to iovdd to set a high level, a pulldown resistor to gnd to set a low level, or open to set a midlevel. for digital control, use three-state logic to drive the three-level logic input. coniguration blocking the deserializer can block changes to registers. set cfgblock to make all registers read only. once set, the registers remain blocked until the supplies are removed or until pwdn is low. compatibility with other gmsl devices the MAX9240A deserializer is designed to pair with the max9271/max9273 serializers, but interoperate with any gmsl serializers. see the table 10 for operating limitations. gpios the deserializer has two open-drain gpios available when not used as configuration inputs. gpio1out and gpio0out (0x0e, d3 and d1) set the output state of the gpios. setting the gpio output bits to 0 pulls the output low, while setting the bits to 1 leaves the output undriven and pulled high through internal/external pullup resistors. the gpio input buffers are always enabled. the input states are stored in gpio1 and gpio0 (0x0e, d2 and d0). set gpio1out/gpio0out to 1 when using gpio1/ gpio0 as an input. staggered parallel outputs the deserializer staggers the parallel data outputs to reduce emi and noise. staggering outputs also reduces the power-supply transient requirements. by default, the deserializer staggers outputs according to table 11 . disable output staggering through the disstag bit (0x08, d3). table 10. MAX9240A feature compatibility MAX9240A feature gmsl deserializer hsync/vsync encoding if feature not supported in the serializer, must be turned off in the deserializer. hamming-code error correction if feature not supported in the serializer, must be turned off in the deserializer. i 2 c-to-i 2 c if feature not supported in the serializer, must use uart-to-i 2 c or uart-to-uart. crc error detection if feature not supported in the serializer, must be turned off in the deserializer. double output if feature not supported in the serializer, the data is inputted as a single word at 1/2 the output frequency. coax if feature not supported in the deserializer, must connect unused serial output through 200nf and 50? in series to avdd and set the reverse control-channel amplitude to 100mv. i 2 s encoding if feature is supported in the serializer, must disable i 2 s in the serializer. MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 38 downloaded from: http:///
local control-channel enable (lccen) the deserializer provides inputs for limited configura - tion of the device when a c is not connected. connect lccen = low upon power-up to disable the local control channel and enable the double-function configuration inputs ( table 12 ). all input configuration states are latched at power-up. line-fault detection the line-fault detector in the deserializer monitors for line failures such as short to ground, short to battery, and open link for system fault diagnosis. figure 4 shows the required external resistor connections. lflt goes low when a line fault is detected and lflt goes high when the line returns to normal. the line-fault failure type is stored in 0x14 d[3:0] of the deserializer. filter lflt with the c to reduce the detectors susceptibility to temporary ground shifts. the fault detector threshold voltages are referenced to the deserializer ground. additional passive components set the dc level of the cable ( figure 4 ). if the serializer and gmsl deserializer grounds are different, the link dc voltage during normal operation can vary and cross one of the fault detection thresholds. table 11. staggered output delay table 12. double-function configuration table 13. line fault mapping output output delay relative to dout0 (ns) disstag = 0 disstag = 1 dout0Cdout5, dout21, dout22 0 0 dout6Cdout10, dout23, dout24 0.5 0 dout11Cdout15 1 0 dout16Cdout20 1.5 0 pclkout 0.75 0 lccen gpio0/dbl function gpio1/bws function ms/hven function rx/sda/edc function tx/scl/es function high functions as gpio functions as gpio ms input (low = base mode, high = bypass mode) uart/i 2 c input/output uart/i 2 c input/output low dbl input (low = single input, high = double input) bws input (low = 24-bit mode, high = 32-bit mode) hven input (low = hs/vs encoding disabled, high = hs/vs encoding enabled) edc input (low = error detection/ correction disabled, high = error detection/ correction enabled) es input (low = valid dout_ on rising edge of pclkout, high = valid dout_ on falling edge of pclkout) register address bits name value line fault type 0x14 d[3:2] lfneg 00 negative cable wire shorted to supply voltage 01 negative cable wire shorted to ground 10 normal operation 11 negative cable wire disconnected d[1:0] lfpos 00 positive cable wire shorted to supply voltage 01 positive cable wire shorted to ground 10 normal operation 11 positive cable wire disconnected MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 39 downloaded from: http:///
for the fault-detection circuit, select the resistors power rating to handle a short to the battery. in coax mode, leave the unused line-fault inputs unconnected. to detect the short-together case, refer to application note 4709 : max9259 gmsl line-fault detection. table 13 lists the mapping for line-fault types. internal input pulldowns the control and configuration inputs, except three-level inputs, include a pulldown resistor to gnd. external pulldown resistors are not needed. choosing i 2 c/uart pullup resistors the i 2 c and uart open-drain lines require a pullup resistor to provide a logic-high level. there are tradeoffs between power dissipation and speed, and a compromise may be required when choosing pullup resistor values. every device connected to the bus introduces some capacitance even when the device is not in operation. i 2 c specifies 300ns rise times (30% to 70%) for fast mode, which is defined for data rates up to 400kbps (see the i 2 c specifications in the ac electrical characteristics table for details). to meet the fast-mode rise-time requirement, choose the pullup resistors so that rise time t r = 0.85 x r pullup x c bus < 300ns. the waveforms are not recog - nized if the transition time becomes too slow. the deserial - izer supports i 2 c/uart rates up to 1mbps (uart-to-i 2 c mode) and 400kbps (i 2 c-to-i 2 c mode). ac-coupling ac-coupling isolates the receiver from dc voltages up to the voltage rating of the capacitor. capacitors at the serializer output and at the deserializer input are needed for proper link operation and to provide protection if either end of the cable is shorted to a battery. ac-coupling blocks low-frequency ground shifts and low-frequency common-mode noise. selection of ac-coupling capacitors voltage droop and the digital sum variation (dsv) of trans - mitted symbols cause signal transitions to start from dif - ferent voltage levels. because the transition time is fixed, starting the signal transition from different voltage levels causes timing jitter. the time constant for an ac-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. the rc network for an ac-coupled link consists of the cml/coax receiver termination resistor (r tr ), the cml/coax driver termination resistor (r td ), and the series ac-coupling capacitors (c). the rc time constant, for four equal-value series capacitors, is (c x (r td + r tr ))/4. r td and r tr are required to match the transmission line impedance (usually 100 differential and 50 single-ended). this leaves the capacitor selection to change the system time constant. use 0.22f or larger high-frequency surface-mount ceramic capacitors, with sufficient voltage rating to withstand a short to battery, to pass the lower speed reverse control-channel signal. use capacitors with a case size less than 3.2mm x 1.6mm to have lower parasitic effects to the high-speed signal. power-supply circuits and bypassing the deserializer uses an avdd and dvdd of 1.7v to 1.9v. all inputs and outputs, except for the serial input, derive power from an iovdd of 1.7v to 3.6v that scales with iovdd. proper voltage-supply bypassing is essential for high-frequency circuit stability. the gpi-to-gpo delay is 0.35ms (max). keep the time between gpi transmissions to a minimum 0.35ms. power-supply table power-supply currents shown in the electrical characteristics table are the sum of the currents from avdd, dvdd, and iovdd. typical currents from the individual power supplies are shown in table 14 . cables and connectors interconnect for cml typically has a differential impedance of 100. use cables and connectors that have matched differential impedance to minimize impedance discontinuities. coax cables typically have a characteristic impedance of 50 (contact the factory for 75 operation). table 15 lists the suggested cables and connectors used in the gmsl link. table 14. typical power-supply currents (using worst-case input pattern) table 15. suggested connectors and cables for gmsl pclk (mhz) avdd (ma) dvdd (ma) iovdd (ma) 25 25.1 9.2 10.3 50 33.3 13.7 13.3 supplier connector cable type rosenberger 59s2ax-400a5-y rg174 coax jae mx38-ff a-bw-lxxxxx stp nissei gt11l-2s f-2wme awg28 stp rosenberger d4s10a-40ml5-z dacar 538 stp MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 40 downloaded from: http:///
board layout separate the lvcmos logic signals and cml/coax high- speed signals to prevent crosstalk. use a four-layer pcb with separate layers for power, ground, cml/coax, and lvcmos logic signals. layout pcb traces close to each other for a 100 differential characteristic impedance. the trace dimensions depend on the type of trace used (microstrip or stripline). note that two 50 pcb traces do not have 100 differential impedance when brought close togetherthe impedance goes down when the traces are brought closer. use a 50 trace for the single-ended output when driving coax. route the pcb traces for differential cml channel in parallel to maintain the differential characteristic impedance. avoid vias. keep pcb traces that make up a differential pair equal length to avoid skew within the differential pair. esd protection esd tolerance is rated for human body model, iec 61000-4-2, and iso 10605. the iso 10605 and iec 61000-4-2 standards specify esd tolerance for electronic systems. the serial link inputs are rated for iso 10605 esd protection and iec 61000-4-2 esd protection. all pins are tested for the human body model. the human body model discharge components are c s = 100pf and r d = 1.5k ( figure 34 ). the iec 61000-4-2 discharge components are c s = 150pf and r d = 330 ( figure 35 ). the iso 10605 discharge components are c s = 330pf and r d = 2k ( figure 36 ). figure 34. human body model esd test circuit figure 35 iec 61000-4-2 contact discharge esd test circuit figure 36. iso 10605 contact discharge esd test circuit storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance 1m ? r d 1.5k ? c s 100pf c s 150pf storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 330 ? storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 2k ? c s 330pf MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 41 downloaded from: http:///
table 16. register table register address bits name value function default value 0x00 d[7:1] serid xxxxxxx serializer device address. 1000000 d0 0 reserved. 0 0x01 d[7:1] desid xxxxxxx deserializer device address. default address is determined by the state of the cx/tp input (table 8). 1001000, 1001001 d0 cfgblock 0 normal operation. 0 1 registers 0x00 to 0x1f are read only. 0x02 d[7:6] ss 00 no spread spectrum. 00 01 2% spread spectrum. 10 no spread spectrum. 11 4% spread spectrum. d[5:4] 01 reserved. 01 d[3:2] prng 00 12.5mhz to 25mhz pixel clock. 11 01 25mhz to 50mhz pixel clock. 10 do not use. 11 automatically detect the pixel clock range. d[1:0] srng 00 0.5gbps to 1gbps serial-data rate. 11 01 1gbps to 1.5gbps serial-data rate. 10 automatically detect serial-data rate. 11 automatically detect serial-data rate. 0x03 d[7:6] autofm 00 calibrate spread-modulation rate only once after locking. 00 01 calibrate spread-modulation rate every 2ms after locking. 10 calibrate spread-modulation rate every 16ms after locking. 11 calibrate spread-modulation rate every 256ms after locking. d5 0 reserved. 0 d[4:0] sdiv 00000 autocalibrate sawtooth divider. 00000 xxxxx manual sdiv setting. see the manual programming of the spread-spectrum divider section. MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 42 downloaded from: http:///
table 16. register table (continued) register address bits name value function default value 0x04 d7 locked 0 lock output is low. 0 (read only) 1 lock output is high. d6 outenb 0 enable pclkout, dout_ and i2s outputs. 0 1 disable pclkout, dout_ and i2s outputs. d5 prbsen 0 disable prbs test. 0 1 enable prbs test. d4 sleep 0 normal mode. 0 1 activate sleep mode. d[3:2] inttype 00 local control channel uses i 2 c when i2csel = 0. 01 01 local control channel uses uart when i2csel = 0. 10, 11 local control channel disabled. d1 revccen 0 disable reverse control channel to serializer (sending). 1 1 enable reverse control channel to serializer (sending). d0 fwdccen 0 disable forward control channel from serializer (receiving). 1 1 enable forward control channel from serializer (receiving). 0x05 d7 i2cmethod 0 i 2 c conversion sends the register address when converting uart to i 2 c. 0 1 disable sending of i 2 c register address when converting uart to i 2 c (command-byte-only mode). d6 dcs 0 normal parallel output driver current. 0 1 boosted parallel output driver current. d5 hvtrmode 0 partial periodic hs/vs tracking. 1 1 full periodic hs/vs tracking. d4 eneq 0 equalizer disabled. power-up default. 0 1 equalizer enabled. d[3:0] eqtune 0000 2.1db equalizer-boost gain. 1001 0001 2.8db equalizer-boost gain. 0010 3.4db equalizer-boost gain. 0011 4.2db equalizer-boost gain. 0100 5.2db equalizer-boost gain. 0101 6.2db equalizer-boost gain. 0110 7db equalizer-boost gain. 0111 8.2db equalizer-boost gain. 1000 9.4db equalizer-boost gain. 1001 10.7db equalizer-boost gain. power-up default. 1010 11.7db equalizer-boost gain. 1011 13db equalizer-boost gain. 11xx do not use. MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 43 downloaded from: http:///
table 16. register table (continued) register address bits name value function default value 0x06 d[7:0] 00000010 reserved. 00000010 0x07 d7 dbl 0 single-input mode. power-up default when lccen = high or gpio0/dbl = low. 0, 1 1 double-input mode. power-up default when lccen = low and gpio0/dbl = high. d6 drs 0 high data-rate mode. 0 1 low data-rate mode. d5 bws 0 24-bit mode. power-up default when lccen = high or gpio1/bws = low. 0, 1 1 32-bit mode. power-up default when lccen = low and gpio1/bws = high. d4 es 0 output data valid on rising edge of pclkout. power-up default when lccen = high or tx/scl/es = low. do not change this value while the pixel clock is running. 0, 1 1 output data valid on falling edge of pclkout. power-up default when lccen = low and tx/scl/es = high. do not change this value while the pixel clock is running. d3 hvtrack 0 hs/vs tracking disabled. power-up default when lccen = high or ms/hven = low. 0, 1 1 hs/vs tracking enabled. power-up default when lccen = low and ms/hven = high. d2 hven 0 hs/vs encoding disabled. power-up default when lccen = high or ms/hven = low. 0, 1 1 hs/vs encoding enabled. power-up default when lccen = low and ms/hven = high. d[1:0] edc 00 1-bit parity error detection (gmsl compatible). power-up default when lccen = high or rx/sda/ edc = low. 00, 10 01 6-bit crc error detection. 10 6-bit hamming code (single-bit error correct, double-bit error detect) and 16-word interleaving. power-up default when lccen = low and rx/sda/edc = high. 11 do not use. MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 44 downloaded from: http:///
table 16. register table (continued) register address bits name value function default value 0x08 d7 invvs 0 no vs or dout0 inversion. 0 1 invert vs when hven = 1. invert dout0 when hven = 0. do not use if dbl = 0 in the deserializer and dbl = 1 in the serializer. d6 invhs 0 no hs or dout1 inversion. 0 1 invert hs when hven = 1. invert dout1 when hven = 0. do not use if dbl = 0 in the deserializer and dbl = 1 in the serializer. d5 0 reserved. 0 d4 uneqdbl 0 serializer dbl is not the same as deserializer. 0 1 serializer dbl same as deserializer (set to 1 only when hven = 0 and hvtrack = 1). d3 disstag 0 enable staggered outputs. 0 1 disable staggered outputs. d2 autorst 0 do not automatically reset error registers and outputs. 0 1 automatically reset deterr and correrr registers 1s after err asserts. d[1:0] errsel 00 err asserts when deterr is larger than detthr. 00 01 err asserts when correrr is larger than corrthr. 10, 11 err asserts when deterr is larger than detthr or correrr is larger than corrthr. 0x09 d[7:1] i2csrca xxxxxxx i 2 c address translator source a. 0000000 d0 0 reserved. 0 0x0a d[7:1] i2cdsta xxxxxxx i 2 c address translator destination a. 0000000 d0 0 reserved. 0 0x0b d[7:1] i2csrcb xxxxxxx i 2 c address translator source b. 0000000 d0 0 reserved. 0 0x0c d[7:1] i2cdstb xxxxxxx i 2 c address translator destination b. 0000000 d0 0 reserved. 0 MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 45 downloaded from: http:///
table 16. register table (continued) register address bits name value function default value 0x0d d7 i2clocack 0 acknowledge not generated when forward channel is not available. 1 1 i 2 c-to-i 2 c slave generates local acknowledge when forward channel is not available. d[6:5] i2cslvsh 00 352ns/117ns i 2 c setup/hold time. 01 01 469ns/234ns i 2 c setup/hold time. 10 938ns/352ns i 2 c setup/hold time. 11 1046ns/469ns i 2 c setup/hold time. d[4:2] i2cmstbt 000 8.47kbps (typ) i 2 c-to-i 2 c master bit-rate setting. 101 001 28.3kbps (typ) i 2 c-to-i 2 c master bit-rate setting. 010 84.7kbps (typ) i 2 c-to-i 2 c master bit-rate setting. 011 105kbps (typ) i 2 c-to-i 2 c master bit-rate setting. 100 173kbps (typ) i 2 c-to-i 2 c master bit-rate setting. 101 339kbps (typ) i 2 c-to-i 2 c master bit-rate setting. 110 533kbps (typ) i 2 c-to-i 2 c master bit-rate setting. 111 837kbps (typ) i 2 c-to-i 2 c master bit-rate setting. d[1:0] i2cslvto 00 64s (typ) i 2 c-to-i 2 c slave remote timeout. 10 01 256s (typ) i 2 c-to-i 2 c slave remote timeout. 10 1024s (typ) i 2 c-to-i 2 c slave remote timeout. 11 no i 2 c-to-i 2 c slave remote timeout. 0x0e d[7:6] 01 reserved. 01 d5 gpien 0 disable gpi-to-gpo signal transmission to serializer. 1 1 enable gpi-to-gpo signal transmission to serializer. d4 gpiin 0 gpi input is low. 0 (read only) 1 gpi input is high. d3 gpio1out 0 set gpio1 to low. 1 1 set gpio1 to high. d2 gpio1in 0 gpio1 input is low. 0 (read only) 1 gpio1 input is high. d1 gpio0out 0 set gpio0 to low. 1 1 set gpio0 to high. d0 gpio0in 0 gpio0 input is low. 0 (read only) 1 gpio0 input is high. 0x0f d[7:0] detthr xxxxxxxx error threshold for detected errors. 00000000 0x10 d[7:0] deterr xxxxxxxx detected error counter. 00000000 (read only) 0x11 d[7:0] corrthr xxxxxxxx error threshold for corrected errors. 00000000 0x12 d[7:0] correrr xxxxxxxx corrected error counter. 00000000 (read only) 0x13 d[7:0] prbserr xxxxxxxx prbs error counter. 00000000 (read only) MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 46 downloaded from: http:///
table 16. register table (continued) register address bits name value function default value 0x14 d7 prbsok 0 prbs test not completed. 0 (read only) 1 prbs test completed with success. d[6:4] 000 reserved. 000 (read only) d[3:2] lfneg 00 negative cable wire shorted to supply voltage 10 (read only) 01 negative cable wire shorted to ground 10 normal operation 11 negative cable wire disconnected d[1:0] lfpos 00 positive cable wire shorted to supply voltage 10 (read only) 01 positive cable wire shorted to ground 10 normal operation 11 positive cable wire disconnected 0x15 d[7:0] 00100xxx reserved. 00100xxx 0x16 d[7:0] 00110000 reserved. 00110000 0x17 d[7:0] 01010100 reserved. 01010100 0x18 d[7:0] 00110000 reserved. 00110000 0x19 d[7:0] 11001000 reserved. 11001000 0x1a d[7:0] xxxxxxxx reserved. 00000000 (read only) 0x1b d[7:0] xxxxxxxx reserved. 00000000 (read only) 0x1c d[7:0] xxxxxxxx reserved. 00000000 (read only) 0x1d d7 cxtp 0 cx/tp input is low. 0 (read only) 1 cx/tp input is high. d6 cxsel 0 cxsel is 0. 0 (read only) 1 cxsel is 1. d5 i2csel 0 input is low. 0 (read only) 1 input is high. d4 lccen 0 input is low. 0 (read only) 1 input is high. d[3:0] xxxx reserved. 0000 (read only) 0x1e d[7:0] id 00001100 device identiier (MAX9240A = 0x0c). 00001100 (read only) 0x1f d[7:5] 000 reserved. 000 (read only) d4 caps 0 not hdcp capable. 0 (read only) 1 hdcp capable. d[3:0] revision xxxx device revision. (read only) MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 47 downloaded from: http:///
+ denotes a lead(pb)-free/rohs-compliant package. /v denotes an automotive qualified part. * ep = exposed pad. ** future productcontact factory for availability. part temp range pin-package MAX9240Agtm+ -40c to +105c 48 tqfn-ep* MAX9240Agtm/v+** -40c to +105c 48 tqfn-ep* package type package code outline no. land pattern no. 48 tqfn-ep t4877+4 21-0144 90-0130 conf1conf0 rx/sda/edc tx/scl/dbl tx/scl/es lccen out+ 49.9k ? 49.9k ? out- dout0Cdout9 pclkout gpi lflt rx/sda/edc lmn1 to peripherals camera application lock din0Cdin9 pclkin note: not all pullup/pulldown resistors are shown. see pin description for details. txrx gpu ecu data pclk gpo pclk data camera fs uart in+in- fs lflt cx/ tp 4.99k ? 45.3k ? 45.3k ? 4.99k ? lmn0 MAX9240A max9271 MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect www.maximintegrated.com maxim integrated 48 typical application circuit package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos ordering information downloaded from: http:///
revision number revision date description pages changed 0 3/14 initial release 1 8/15 corrected typos and unclear text in data sheet 1C48 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. MAX9240A 6.25mhz to 100mhz, 25-bit gmsl deserializer for coax or stp cable with line fault detect ? 2015 maxim integrated products, inc. 49 revision history for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

▲Up To Search▲

Price & Availability of MAX9240A

	To Download MAX9240A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .